1. Field of the Invention
The present invention relates to a method of manufacturing an insulated gate field effect transistor (hereinafter abbreviated as IGFET), and more particularly, to a method of manufacturing an IGFET in which each of the source and drain regions is composed of a first region having a low impurity concentration and facing to a channel region and a second region having a high impurity concentration and positioned between the first region and a field region.
2. Description of the Prior Art
When an IGFET is reduced in size into minute dimensions and the channel length is shortened, a hot electron effect is produced due to rise of an electric field intensity within the channel region. Accordingly, shortening of the channel length as well as an available power supply voltage are limited. In order to resolve this problem, an IGFET in which one portions of the source and drain regions adjacent to the channel region were made to have a lower impurity concentration than the other portions, was proposed. This technique is disclosed in "IEEE TRANSACTIONS ON ELECTRON DEVICES" Vol. Ed-27, No. 8, August 1980, pp. 1359 to 1367 and "IEEE TRANSACTIONS ON ELECTRON DEVICES" Vol. Ed-29, No. 4, April 1982, pp. 590 to 596.
The former literature discloses a method in which N-type ions are injected into a P-type semiconductor substrate up to a high concentration by making use of a silicon gate electrode, a silicon nitride film on the gate electrode and a silicon oxide film thereon as a mask and then the silicon gate electrode is side-etched. Thereafter the silicon nitride film and silicon oxide film thereon are removed, and N-type impurity ions are injected into the semiconductor substrate up to a low impurity concentration by making use of the silicon gate electrode that was shortened by the side-etching as a mask. By the above-mentioned method, the portions of the source and drain regions adjacent to the channel region which is positioned under the shortened gate electrode would have a low impurity concentration over the extent corresponding to the side-etched distance of the silicon gate electrode.
However, the above-mentioned side-etching process has a large deviation in the amount of side-etching regardless of whether a wet-etching process or an isotropic dry-etching process may be employed. For instance, when a polycrystalline silicon gate electrode of 6000 .ANG. in film thickness was subjected to side-etching by means of a HNO.sub.3 :HF series misture, an average amount of side-etching l was 0.33 .mu.m. And when the absolute values of the differences between the amounts of etching of the respective samples and the average amount of etching l were added and then divided by the number of the samples and the quotient was represented by .DELTA.l, the ratio of .DELTA.l/l was about 5%. It is to be noted that in the experiments for measuring the above-defined deviation of side-etching, four semiconductor wafers were processed under the same conditions, and 36 samples were extracted from the semiconductor wafers. The generation of a deviation of about 5% in the amount of side-etching even under the same processing conditions, implies that in the length of the region having a low impurity concentration adjacent to the channel region also, a deviation of about 5% is produced, and so, through such a method, IGFET's having a stable quality cannot be obtained. Moreover, in the case of employing side-etching as described above, the etching would proceed along grain boundaries of the polycrystalline silicon gate electrode, and hence there is a fear that the side surface configuration of the gate electrode may be deteriorated.
On the other hand, in the method disclosed in the latter literature above, at first N-type impurity ions are injected into a P-type semiconductor substrate up to a low concentration by using a polycrystalline silicon gate electrode as a mask. Subsequently, a silicon dioxide film is deposited over the entire substrate through a C.V.D. process, and then subjected to a reactive anisotropic plasma etching to form the so-called side walls from the silicon dioxide film on the opposite side surfaces of the gate electrode. Next, N-type impurity ions are injected into the substrate up to a high concentration by making use of the side walls and the gate electrode as a mask to leave the portions adjacent to the channel regions of the source and drain regions and having a low impurity concentration below the side walls. The length of these regions are therefore determined by the thickness of the side walls. However, the deviation of the thickness of the side walls is large. For instance, a silicon gate electrode of 4000 .ANG. in film thickness was shaped in configuration, and the side surfaces and upper surface of this silicon gate electrode was covered with a thin silicon oxide film of 200 .ANG. to 500 .ANG. in film thickness through thermal oxidation. Subsequently, a silicon dioxide film of 4000 .ANG. in film thickness was deposited over the entire substrate through a C.V.D. process, and then anisotropic reactive ion etching was performed. In the case of this experiment also, four semiconductor wafers were processed under the same conditions, and 36 samples were extracted from the semiconductor wafers. In this case, the length of the silicon gate electrode was varied to different values in the range of 1.0 to 2.0 .mu.m. The thickness of the side walls is independent of the length of the silicon gate electrode and is dependent upon the thickness of the silicon gate electrode. As a result of the above-described experiments and measurements, an average thickness of the side walls L was proved to be 0.27 .mu.m. Assuming now that the quotient of the total of the absolute values of the differences between the thickness of the side wall in the respective samples and the average thickness L divided by the number of the samples, is represented by .DELTA.L, then the ratio of .DELTA.L/L was as large as 18.4%. This implies that if the above-mentioned method is employed, a large deviation of about 18% would be produced in the length of the region adjacent to the channel region having a low impurity concentration even under the same conditions of processing, and so IGFET's having a stable quality cannot be obtained. Moreover, the repeated use of reactive ion etching as described above would damage the surfaces of the semiconductor substrates and would adversely affect the performance of the manufactured IGFET.